Most single-ended source synchronous open-drain communication interfaces, such as I2C, use a dedicated clock or strobe signal line to send cycle timing information from a transmitter to a receiver. Certain disadvantages are associated with these signaling systems, including a requirement for one extra signal dedicated for clock information. Maximum data rate is often limited when single-rate signaling is used such that one data symbol sent for each full clock period consisting of a clock high and clock low cycle, whereby the maximum data rate is often limited by a maximum allowed frequency of the system clock rather than the maximum allowed frequency of the data line. The maximum data rate is also often limited by skew between the clock and data that can be hard to control for optimal signaling.
In some instances, to avoid the use of a dedicated clock line, a clock may be embedded by guaranteeing symbol-to-symbol transitions within transmitted data symbols. Thus, a receiver device may extract clock information from the detection of symbol-to-symbol transitions. However, reliable or consistent detection of transitions by a receiver's logic may be affected by rise times and fall times of the transmitted signal. 1
Unlike complementary metal-oxide-semiconductor (CMOS) push-pull drivers, open-drain type drivers have a signal rise time that is significantly longer than a signal fall time. This difference in rise and fall times for open-drain type drivers poses a problem for clock recovery from transmitted data symbols as some transitions may be missed.
Therefore, a solution is needed that permits extracting a clock from transmitted data symbols without slowing down the data transmission rate.